Design, modeling and simulation of junction less fin fet

In this paper Junction Less Fin-type Field Effect Transistor (JL Fin-FET) has been optimally designed and characterized by using SILVACO device simulator. Fin-FETs are promising substitutes for bulk Complementary Metal Oxide Semiconductor (CMOS) at the Nano scale. Fin-FET can be a designed double-gate device, the two gates of a Fin-FET can either be shorted for higher performance or independently controlled for lower leakage or reduced transistor count. This gives rise to a rich design space. Here, the high-k/metal-gate technology is adopted to enhance the gate controllability, prevent the gate leakage current. The design and modeling is done as per the CMOS process. The Fin-FET is simulated using different channels and for each channel drain characteristics are observed. The gate terminal is also designed with different thin oxide materials, which are having high dielectric coefficient and different band gap, the results show that in fast switching speed of operation, which will primarily helpful for memory cells and low power VLSI circuits.